Microprocessor systems may use various forms of busses to exchange data. It is convenient to generically label the various functional elements of the system that are connected to the bus, such as processors, memory controllers, input/output controllers, or chipsets, as bus “agents”. In a simplified bus system, a requesting agent may send a request message over the bus, and a responding agent with the requested data may respond with a data message to the requesting agent. In such a simplified bus design, the bus would stay in an idle state after the issuance of the request message until the corresponding data message was sent. When a long-latency operation occurs, such as a responding agent having to fetch data from a system memory, the idle state could occupy a significant period of time. Such idle states would therefore not permit efficient use of the limited bus bandwidth.
In order to avoid the use of such idle states on the bus, various bus designs have been implemented that permit other bus transactions to occupy the time periods between a data request message and the corresponding data message. One such bus design has used what is sometimes referred to in the technical literature as an “enhanced defer protocol”. In this protocol, when the responding agent will not gain access to the requested data in a short period of time, it quickly issues a deferred response message. This deferred response message indicates to the requesting agent that the request was correctly received but that the responding agent does not yet have the data. Then when the responding agent does receive the data, it may arbitrate for the bus and then send concurrently an identification signal and a data signal. The identification signal and data signal, arriving together, give the data requested and also logically connect it to the correct pending request.
For further details of a bus implementing an enhanced defer protocol, see U.S. Pat. No. 6,012,118 to Muthurajan Jayakumar, et al, which issued on 4 Jan. 2000.